Analog Circuit Design: Scalable Analog Circuit Design, by Johan Huijsing, Michiel Steyaert, Arthur H.M. van Roermund

By Johan Huijsing, Michiel Steyaert, Arthur H.M. van Roermund

This 10th quantity of Analog Circuit layout concentrates on three subject matters: 1. Scalable Analog Circuits, 2. High-Speed D/A Converters, and three. RF energy Amplifiers. every one subject is roofed via 6 papers, written by means of the world over well-known specialists on that subject. those papers have an instructional nature aimed toward enhancing the layout of analog circuits. The ebook is split into 3 components: half I, Scalable Analog Circuit layout describes in 6 papers problems with: scalable high-speed layout, scalable high-resolution mixed-mode ADC and OpAmp layout, scalable high-voltage layout for XDSL, scalability of wire-line entrance ends, reusable IP analog layout, and porting CAD analog layout. half II, High-Speed D/A Converters describes in 6 papers problems with: advent to high-speed D/A converter layout, retargetable 12-bit 200-MHz CMOS present guidance layout, high-speed CMOS D/A converters for upstream cable purposes, static and dynamic functionality barriers, the linearity problem of D/A converters for communications, and a 400-MHz, 10-bit charge-domain CMOS D/A converter for low-spurious frequency synthesis. half III, RF strength Amplifiers describes in 6 papers problems with: process facets, review and trade-offs, linear transmitter architectures, GaAs microwave SSPAs, Monolithic transformer-coupling in Si-bipolar, and RF energy amplifier layout in CMOS.

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A further improvement is to incorporate the passive current filtering network shown between the demodulator and the integrator. Analysis will show that this network has a band-stop current transfer function with zero phase shift at a selected high frequency (Fig. 8), chosen to be the amplifier’s unity gain frequency. 39 In this example, optimised for an opamp with unity gain bandwidth of 40MHz and a maximum signal frequency of 1 MHz, it is seen that the effect of the filter is to permit a factor 3 reduction in integrator time constant to give 3x loop gain increase at the maximum signal frequency with zero phase loss at the unity gain bandwidth.

On the contrary, a DMOS component (see Figure 4) is capable of working at a breakdown voltage Beds equal to the Bacon of the parasitic nun component provided that the base to emitter short circuit is good enough. To some extend, DMOS capable junction isolated technologies feature small component size. As an additional advantage (see in the following), DMOS technologies can also be made compatible with CMOS transistors that, in its turn, can enable the realization of highly complex mixed ICs. 51 INTEGRATION OF HIGH VOLTAGE DMOS HIGH COMPONENTS INTO SUBMICRON TECHNOLOGIES.

IEEE Jnl. of Solid State Circuits, Vol. 32, pp. 1896-1906, Dec. 1997 18) “Tree Structure for Mismatch Noise-Shaping Multibit DAC” Keady and Lyden, Elec. Letters, Vol. 33, pp. 1431-1432, Aug. , Proc. European Solid-State Circuits Conference, Southampton, 1997 20) “Delta-Sigma Data Converters” Norsworthy, Schreier and Temes, IEEE Press, 1997 21) “A Monolithic 19 bits 800kHz Low Power Multibit Sigma Delta Modulator CMOS ADC Using Data Weighted Averaging” Nys and Henderson, Proc. European Solid-State Circuits Conference, pp.

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